The present invention relates to a semiconductor device, and can be preferably used for a semiconductor device having a metal wiring formed by, for example, a damascene process.
Japanese Unexamined Patent Application Publication No. 2002-343861 describes a semiconductor integrated circuit in which the upper surface of a contact plug located at the end opposite to the lower surface thereof projects from the main surface of an interlayer insulating film and a capacitor lower electrode is arranged, while the center thereof is deviated, at an upper portion of the contact plug so as to cover a projection part of the contact plug.